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M34C00
3 x 128 bit Serial IC Bus EEPROM For ee-Tags
PRELIMINARY DATA
s
Two-Wire I2C Serial Interface Supports 400 kHz Protocol 2.5 V to 5.5 V Single Supply Voltage 384-bit EEPROM divided in three areas: - 128 bits of non-erasable memory - 128 bits of standard EEPROM - 128 bits that can be permanently Writeprotected (to behave as ROM)
s s
8 1
SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width
s s s s
Self-Timed Program Cycle Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
DESCRIPTION The M34C00 is a 384-bit serial EEPROM. The bottom third of the memory area (from location 00h to 0Fh) can be Write-protected using a specially designed software Write-protection mechanism. By sending the device a specific sequence, the first 128 bits of the memory become permanently Write-protected. Care must be taken when using this sequence as its effect cannot be reversed. The top third of the memory area (from location 20h to 2Fh) is already configured to give the functional equivalence of a non-erasable memory. That is, it is initialized to all 1s (FFh), and the user is able to reset any number of those 1s to 0; but there is no mechanism for the user to set a 0 back to a 1. The M34C00 is a 384-bit electrically erasable programmable memory (EEPROM), organized as 48 x 8 bits.
Figure 1. Logic Diagram
VCC
SCL
M34C00
SDA
Table 1. Signal Names
SDA SCL VCC VSS Serial Data Serial Clock Supply Voltage Ground
VSS
AI03394
August 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M34C00
Figure 2A. SO and TSSOP Connections When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) This signal is used to strobe all data in and out of the device. In applications where this line is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open
M34C00 NC NC NC VSS 1 2 3 4 8 7 6 5
AI03395B
VCC NC SCL SDA
Note: 1. NC = Not Connected
These devices are compatible with the I2C memory standard. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition to access the memory area and a second Device Type Identifier code (0110) to access the Protection Register. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature
Value -40 to 85 -65 to 150 t.b.d. 235 235 -0.6 to 6.5 -0.3 to 6.5 4000
Unit C C C V V V
SOT23: t.b.d. Lead Temperature during Soldering SO: 20 seconds (max) 2 TSSOP: 20 seconds (max) 2 Input or Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model) 3
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. IPC/JEDEC J-STD-020A 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
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Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). DEVICE OPERATION The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M34C00 device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a programming cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Table 3. Device Select Code
Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable, and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the data on Serial Data (SDA)
Device Type Identifier1 b7 Memory Area Select Code (three arrays) Protection Register Select Code
Note: 1. The most significant bit (b7) is sent first.
RW b4 0 0 b3 1 1 b2 1 1 b1 1 1 b0 RW RW
b6 0 1
b5 1 1
1 0
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M34C00
Figure 4. I2C Bus Protocol
SCL
SDA SDA Input SDA Change
START Condition
STOP Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START Condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP Condition
AI00792B
must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the 8-bit byte, shown in Table 3, on Serial Data (SDA) (most significant bit first). This consists of the 7-bit Device Select code, and the Read/Write bit (RW). To address the memory array, the 4-bit Device Type Identifier is 1010b. To address the Protection Register, it is 0110b, as shown in Table 3. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it
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deselects itself from the bus, and goes into Standby mode. Memory Partitioning The memory is divided in three arrays: s Array-0: Write-protectable Array (00h to 0Fh)
s s
Array-1: EEPROM Array (10h to 1Fh) Array-2: Non-Erasable Memory Array (20h to 2Fh)
The 4 least significant bits of the address byte determine the byte that is to be addressed within the given array. The next 2 more significant address bits determine the array that is to be addressed (Array-0, Array-1, Array-2 or Invalid). The 2 most significant address bits are Don't Care. If the address is of the form xx11xxxx, the device recognises that an attempt is being made to
M34C00
Figure 5. Memory Partitioning
2Fh Array 2 EPROM Array 20h 1Fh Array 1 Standard Array 10h 0Fh Array 0 Standard Array 00h Default EEPROM memory area state before write access to the Protection Register Array 0 Array 1 Standard Array Write Protected Array Array 2 EPROM Array
2Fh
20h 1Fh
10h 0Fh
00h
State of the EEPROM memory area after write access to the Protection Register
AI03396
address the Invalid array, and immediately deselects itself. The Write-protectable array consists of 16 bytes of EEPROM, which can be used as normal EEPROM until this array is set in its Write-protected mode. Once Write-protected, this array becomes functionally equivalent to a Read-Only Memory (ROM), and cannot be modified further. The procedure to set this array in its Write-protected mode is described later. Array-2 also consists of 16 bytes of EEPROM, but configured to give the functional equivalence of non-erasable memory. That is, it is initialized to contain all 1s (FFh), with the user able to reset any 1 to a 0, but unable to set any 0 to a 1. One application envisaged for this array is as a nonresettable 128-token array. WRITE AND READ OPERATIONS Write Operations Following a Start condition the bus master sends a Device Select code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 6, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. Byte Write After the Device Select code and the address byte, the bus master sends one data byte. If the addressed location is in the Write-protected area,
the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not in a Write-protected area, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 6. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 6, but the typical time is shorter. To make use of this, an Ack polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: - Initial condition: a Write cycle is in progress. - Step 1: the bus master issues a Start condition followed by a Device Select code (the first byte of the new instruction). - Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1).
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M34C00
Figure 6. Byte Write Sequences (showing differences in Acknowledge bits)
ACK BYTE WRITE in Array-1 and Array-2 (and in Array-0, if unprotected) DEV SEL START R/W ACK DATA IN STOP NO ACK NO ACK BYTE ADDR R/W DATA IN STOP ACK
BYTE ADDR
ACK BYTE WRITE in Array-0, if protected START DEV SEL
AI03715B
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress (to be followed by a READ) WRITE Cycle in Progress (to be followed by a WRITE)
START Condition DEVICE SELECT with RW = 1
START Condition DEVICE SELECT with RW = 0
No
ACK Returned Yes Read Data Byte
No
ACK Returned Yes
No
Next Operation is a Write Yes
No
Continue the Sequential Read Yes
ReSTART Send Address Byte STOP
NoACK ACK STOP
ACK
Send Data Byte
ACK
STOP
AI03716B
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M34C00
Read Operation Following a Start condition, the bus master sends a Device Select code with the RW bit set to 1. The device acknowledges this, and outputs the byte in location 00h. The counter is then incremented, and the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte output, and must generate a Stop condition, as shown in Figure 8. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the internal address counter rolls over, to continue reading from the start of the memory. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not pull Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Stand-by mode. Setting the Write-Protection by Writing to the Protection Register The M34C00 has a software Write-protection function, using the Protection Register, that allows the bottom 16 bytes of the memory area (addresses 00h to 0Fh) to be permanently WriteTable 4. Write Time
Write Time1 WRITE to Array-0 (when not protected) WRITE to Array-0 (when Write-protected) WRITE to Array-1 WRITE to Array-2
Note: 1. For the value to t W please see Table 6.
tW 0 tW tW
protected. The Write-protection feature is activated by writing once to the Protection Register. The Protection Register is written with the device select code set to 0110.1110b (as shown in Figure 9). Address and data bytes must be sent with this command, but their values are all ignored, and are treated as Don't Care. Once the Protection Register has been written, the Write-protection of the first 16 bytes of the memory is enabled, and it is not possible to unprotect these 16 bytes, even if the device is powered off and on. When the Protection Register has been written, the M34C00 no longer responds to the device type identifier 0110b for either Read or Write operations.
Figure 8. Read Sequence
ACK SEQUENTIAL READ of first N bytes START DEV SEL R/W DATA 0
ACK
ACK
NO ACK DATA N-1 STOP
AI03717
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M34C00
Figure 9. Setting the Protection Register
If the Protection Register has not yet been set: Device Select Byte Address Code RW Don't Care Start Stop ACK NoACK Stop Data In
SDA ACK If the Protection Register has already been set:
Don't Care
ACK
Device Select Byte Address Code RW Don't Care
Start
Data In
SDA
Don't Care
NoACK
NoACK
AI03718
Reading the Protection Register To determine whether the Write-protection feature has been activated, it is possible to read the Protection Register, as shown in Figure 10. - If the Protection Register has not been set, the device acknowledges the read sequence - If the Protection Register has been set, the device deselects itself after it has received the device select code. Consequently, each part of the sequence is not acknowledged.
Figure 10. Reading the Protection Register
If the Protection Register has not yet been set: Device Select Code RW Start Stop NoACK NoACK Stop Data Out
SDA ACK If the Protection Register has been set: Device Select Code RW Start
FFh
Data Out
SDA NoACK
FFh
AI03719B
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M34C00
Table 5. DC Characteristics (TA = -40 to 85 C; VCC = 2.5 to 5.5 V)
Symbol ILI ILO Parameter Input Leakage Current SCL, SDA Test Condition 0 V VIN VCC 0 V VOUT VCC, SDA in Hi-Z VCC =5.5V, fc=400kHz (rise/fall time < 30ns) ICC Supply Current VCC =2.5V, fc=400kHz (rise/fall time < 30ns) Supply Current (Stand-by) Input Low Voltage Input High Voltage Output Low Voltage SCL, SDA SCL, SDA IOL = 3 mA, VCC = 5.5 V IOL = 2.1 mA, VCC = 2.5 V VIN = VSS or VCC , VCC = 5.5 V VIN = VSS or VCC , VCC = 2.5 V -0.3 0.7VCC 1 2 1 0.3VCC VCC+1 0.4 0.4 mA A A V V V V Min. Max. 2 2 2 Unit A A mA
Output Leakage Current
ICC1
VIL VIH
VOL
Table 6. AC Characteristics
M34C00 Symbol Alt. Parameter VCC=2.5 to 5.5V TA = -40 to 85C Min tCH1CH2 tCL1CL2 tDH1DH2 2 tDL1DL2 2 tCHCL tCLCH tCHDX 1 tDLCL tDXCX tCLDX tCHDH tDHDL tCLQV 3 tCLQX fC tW tR tF tR tF tHIGH tLOW tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF tAA tDH fSCL tWR Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock Pulse Width High Clock Pulse Width Low START Set-up Time START Hold Time SDA In Set-up Time SDA In Hold Time STOP Set-up Time Time the bus must be free between STOP and next START Clock Low to SDA Out Valid SDA Out Hold Time after Clock Low Clock Frequency Write Time 20 20 600 1.3 600 600 100 0 600 1.3 200 200 400 10 900 Max 300 300 300 300 ns ns ns ns ns s ns ns ns s ns s ns ns kHz ms Unit
Note: 1. For a reStart condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
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M34C00
Figure 11. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages <= 50 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC 0.2VCC 0.8VCC 0.7VCC 0.3VCC
AI03766
Table 7. Input Parameters 1(T A = 25 C, f = 400 kHz)
Symbol CIN CIN tNS Parameter Input Capacitance (SDA) Input Capacitance (other pins) Pulse width ignored (Input Filter on SCL and SDA) Single glitch 100 Test Condition Min. Max. 8 6 500 Unit pF pF ns
Note: 1. Sampled only, not 100% tested.
Figure 12. AC Waveforms
tCHCL tCLCH
SCL tDLCL SDA In tCHDX START Condition SDA Input tCLDX SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition
SCL
SDA In tCHDH STOP Condition tW Write Cycle tCHDX START Condition
SCL tCLQV SDA Out Data Valid tCLQX
AI00795C
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M34C00
Table 8. Ordering Information Scheme
Example: M34C00 -W MN 6 T
Operating Voltage W 2.5 V to 5.5 V T
Option Tape and Reel Packing
Package MN DW SO8 (150 mil width) TSSOP8 (169 mil width) 6
Temperature Range -40 C to 85 C
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all 1s (FFh), and the Protection Register set at all 0s (00h). The notation used for the device number is as shown in Table 8. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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M34C00
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: Drawing is not to scale.
SO8 narrow - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
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M34C00
TSSOP8 - 8 lead Thin Shrink Small Outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8-M
Note: 1. Drawing is not to scale.
TSSOP8 - 8 lead Thin Shrink Small Outline
mm Symbol Typ. A A1 A2 b c CP D e E E1 L L1 3.000 0.650 6.400 4.400 0.600 1.000 0 8 2.900 - 6.200 4.300 0.450 1.000 0.050 0.800 0.190 0.090 Min. Max. 1.200 0.150 1.050 0.300 0.200 0.100 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295 inches
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M34C00
Table 9. Revision History
Date 05-Jan-2000 16-Oct-2000 Rev 1.0 1.1 Document written Wording changes, according to the standard glossary Explanation of Writing to the Protection Register, and Reading from it Addition of the SOT23-5 package on pp 1, 2, ordering info, and mechanical data SOT23 Connections modified Paragraphs added on Don't Care bits in the address byte, and the effect of address in the Invalid array Attempts to read beyond the end of the memory cause roll-over to occur Reading the protection register does not involve sending an address byte Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated Package mechanical data updated for TSSOP8 package according to JEDEC\MO-153 Document promoted from "Product Preview" to "Preliminary Data" status SOT23-5 package removed Description of Revision
26-Feb-2001
1.2
08-Jun-2001
1.3
27-Aug-2001
1.4
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M34C00
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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